Qualcomm hasn’t given out L2 cache details for the small A510 cores but we do know that Qualcomm is making use of the microarchitecture’s new “merged-core” capabilities, which sees two cores sharing a NEON/SIMD pipeline and L2 cache in this instance. ![]() Although there is a larger 6MB 元 cache, up from 4MB in the previous generation, which will definitely help keeps these new cores fed. That’s the same cache setup as last year, which perhaps explains the performance target being a little lower than Arm’s maximum claims for the X2. ![]() Qualcomm has paired the Cortex-X2 with 1MB of L2 cache and there’s a 512KB cache for each of the A710 cores.
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